Interleaved Host Reset and Next Re-Initialization Operations

ABSTRACT

Embodiments of the present disclosure seek to mitigate the timing issues of prior approaches by performing the NVMe device reset and post-reset re-initialization in parallel. In embodiments, the NVMe device reset and re-initialization operations are logically divided into front-end and back-end operations that may be carried out in parallel. Upon receipt of the command from a host to reset, the NVMe device carries out front-end reset operations for resetting the device, and in parallel performing back-end reinitialization operations. Once the front-end reset operations are complete, or after a predetermined period of time, the NVMe device reports to the host that the device reset is complete, while back-end operations continue. Once all reset and reinitialization operations are complete, the NVMe device may continue to conduct I/O instructions from the host.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of co-pending U.S. patent applicationSer. No. 16/600,816, filed Oct. 14, 2019, which is herein incorporatedby reference.

BACKGROUND OF THE DISCLOSURE Field of the Disclosure

Embodiments of the present disclosure generally relate to theadministration of a data storage, and more particularly to reset of anNVMe device.

Description of the Related Art

During the operation of a host system containing a non-volatile memoryexpress (NVMe) data storage device, occasionally the NVMe is required toundergo a reset operation.

There are two main phases that make up such a reset operation. The firstis the device reset handling. During reset handling, a number ofoperations are carried out, including but not limited to cessation ofcurrently outstanding administrative or I/O processes, deletion of I/Osubmission and completion queues, transition of the NVMe controller isbrought to an idle state, flush of all cached data to the NAND, and anupdate to FTL tables in preparation for the next operation.

Once the reset operations are completed, the NVMe device isreinitialized, the second phase of NVMe device reset begins. The deviceis reinitialized by the host with a number of operations such as updateto register state, configuration of the NVMe controller, creation of I/Ocompletion and submission queues, and once these are complete,continuation of normal I/O operation of the NVMe.

However, the reset and re-initialization processes are typically carriedout in serial. Because it is not known how long the reset and/orre-initialization phases may take, it is unknown how long the entireprocess will take. Because this time is unknown, the NVMe reset process,followed by re-initialization, may not meet standards based expectationsof a host system. Such standards may include NVMe, PCIe, and/or otherstandards for the utilization of memory hardware.

What is needed is a system and method to reset an NVMe device in amanner that is more predictable in terms of time and compliant withstandards.

SUMMARY OF THE DISCLOSURE

Embodiments of the present disclosure seek to mitigate the timing issuesof prior approaches by performing NVMe, PCIe, or other device reset andpost-reset re-initialization in parallel. In embodiments, the NVMedevice reset and re-initialization operations are logically divided intofront-end and back-end operations that may be carried out in parallel.Upon receipt of the command from a host to reset, the NVMe devicecarries out front-end reset operations for resetting the device, and inparallel performing back-end reinitialization operations. Once thefront-end reset operations are complete, or after a predetermined periodof time, the NVMe device reports to the host that the device reset iscomplete, while back-end operations continue. Once all reset andreinitialization operations are complete, the NVMe device may continueto conduct I/O instructions from the host.

In one embodiment, a data storage device is disclosed. In embodiments,the data storage device may include a controller comprising instructionsthat, when executed by a processor, cause the controller to perform amethod of resetting the data storage device. In embodiments, the methodcomprises logically separating a set of front-end reset tasks from a setof back-end reset tasks, receiving a reset command from a host system,performing the set of front-end reset tasks and set of back-end resettasks in parallel upon receipt of the reset command. The method mayfurther comprise transmitting a reset complete signal to the host systemupon completion of the set of front-end reset tasks, and transmitting astorage device ready signal to the host system that indicates that thestorage device is in a condition to receive a command from the hostsystem. In embodiments, the method may further comprise receiving acommand from the host system and executing the command when the set ofback-end reset tasks are complete.

In another embodiment, a data storage system is disclosed. The datastorage system, in embodiments, includes an interface configured toreceive reset instructions from a host, a front-end module configured tocarry out front-end reset operations, and a back-end module configuredto carry out back-end reset operations. This system may further comprisea reset handler module configured to logically separate the front-endmodule from the back-end module, wherein the front-end reset operationsand back-end reset operations are carried out in parallel, and the resethandler module is configured to communicate with the host that resetoperations are complete upon completion of front-end operations.

In another embodiment, a data storage system is disclosed comprising acontroller that includes a processor for executing computer instructionsto reset the data storage system. In embodiments, the controller mayinclude a front-end module configured to carry out front-end resetoperations, a back-end module configured to carry out back-end resetoperations, and a means for logically separating the front-end resetoperations from the back-end reset operations, such that the front-endreset operations and back-end reset operations are carried out inparallel.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentdisclosure can be understood in detail, a more particular description ofthe disclosure, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlytypical embodiments of this disclosure and are therefore not to beconsidered limiting of its scope, for the disclosure may admit to otherequally effective embodiments.

FIG. 1 depicts an NVMe device in accordance with one or moreembodiments.

FIG. 2 depicts a flow diagram describing an interleaved NVMe reset andre-initialization in accordance with one or more embodiments.

FIG. 3 depicts an exemplary processing system for interleaved resettingand reinitializing of an NVMe device, in accordance with one or moreembodiments.

FIG. 4 depicts an exemplary timing diagram in accordance with disclosedembodiments.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures. It is contemplated that elements disclosed in oneembodiment may be beneficially utilized on other embodiments withoutspecific recitation.

DETAILED DESCRIPTION

In the following, reference is made to embodiments of the disclosure.However, it should be understood that the disclosure is not limited tospecific described embodiments. Instead, any combination of thefollowing features and elements, whether related to differentembodiments or not, is contemplated to implement and practice thedisclosure. Furthermore, although embodiments of the disclosure mayachieve advantages over other possible solutions and/or over the priorart, whether or not a particular advantage is achieved by a givenembodiment is not limiting of the disclosure. Thus, the followingaspects, features, embodiments and advantages are merely illustrativeand are not considered elements or limitations of the appended claimsexcept where explicitly recited in a claim(s). Likewise, reference to“the disclosure” shall not be construed as a generalization of anyinventive subject matter disclosed herein and shall not be considered tobe an element or limitation of the appended claims except whereexplicitly recited in a claim(s).

Embodiments of the present disclosure seek to mitigate the timing issuesof prior approaches by performing the NVMe device reset and post-resetre-initialization in parallel. In embodiments, the NVMe device reset andre-initialization operations are logically divided. Reset operations aredivided into front-end and back-end operations, with back-end resetoperations being carried out in parallel with reinitializationoperations. Upon receipt of the command from a host to reset, the NVMedevice carries out front-end reset operations for resetting the device.Once the front-end reset operations are complete, or after apredetermined period of time, the NVMe device reports to the host thatthe device reset is complete, while device reinitialization and back-endoperations continue. Once all reset and reinitialization operations arecomplete, the NVMe device may continue to conduct I/O instructions fromthe host.

FIG. 1 depicts an exemplary NVMe device 100. The NVMe device 100 may beany type of non-volatile memory storage device, however embodimentsdisclosed herein may be applicable to other types of data storagedevices. Suitable means for NVMe device 100 includes solid-state drives(SSD), and may include other storage devices that utilize non-volatileand/or volatile memory.

NVMe device 100 includes an NVMe device controller 105 in accordancewith embodiments. NVMe device controller 105 includes a reset handler110. Reset handler 110 includes a reset handler processor 111 andinstructions capable of managing reset operations for the NVMe devicecontroller 105. Suitable means for the management of reset operationsmay be implemented in hardware, firmware, software, or other mediumcapable of storing instructions that may be read by the reset handler110. Reset handler 110 in some embodiments further includes resethandler evaluation 112, for evaluating time to report reset complete toa host 130.

Reset handler 110 communicates with a front-end 115 and a back-end 120.In addition to controlling the operations of the front-end 115 andback-end 120, the reset handler 110 serves to functionally and/orlogically separate the functioning of each of these components. Asdiscussed below, front-end 115 is configured to carry out resetoperations as well as device reinitialization operations. Reset handler110 in embodiments is configured to logically separate these functionsof the front-end 115 as well. Logical separation in embodiments may becarried out at the architecture level of the NVMe device 100.

Front-end 115 includes a front-end processor 116 as well as a number ofregisters such as NVMe registers 117, and in some embodiments mayinclude PCI configuration space 118. Front-end 115 includes componentsresponsible for interaction with the host 130, such as PCIe, PHY, MAC,NVMe, and processors such as front-end processor 116. Front-end 115 maybe configured to carry out a number of reset operations, includingcessation of currently outstanding administrative or I/O processes,deletion of I/O submission and completion queues, transition of the NVMecontroller is brought to an idle state, flush of all cached data to theNAND, update to FTL tables in preparation for the next operation,cleaning up internal database tables (e.g. collision tables), resettingall status and configuration registers, cleaning the data path, and thelike. In embodiments, front-end 115 is configured to reinitialize theNVMe device 100. Reinitialization in embodiments includes, and is notlimited to, re-establishing the link to the a host coupled to NVMedevice 100, PCIe enumeration and initialization, NVMe registerreinitialization, recreation of NVMe queues, and MSI-X tableinitialization.

Back-end 120 includes a back-end processor 121, and components thatintegrate modules responsible for interactions with memories such as DMA122, as well as components that ensure data integrity such as errorcorrection 123. Back-end 120 in embodiments includes connections to oneor more NANDs and one or more memories (e.g. DDR memory), that may beaccessed during back-end reset operations. Back-end 120 is configured tocarry out reset operations such as flushing all cache data to the NAND,updating tables in the NAND, cleaning the internal databases, resettingall status and configuration registers, and other background operations.

The host 130 utilizes the NVMe device 100 controlled by the NVMe devicecontroller 105 in the execution of I/O operations. The host 130 may beany type of compute system capable of using NVMe device 100. Suitablemeans for a host include a portable compute device, adesktop/workstation computer, a distributed compute system, avirtualized compute system, or any type of compute system capable ofusing NVMe device 100.

Upon receiving a reset command, in some embodiments the NVMe devicecontroller 105 evaluates via reset handler evaluation 112 of the resethandler 110, when to notify the host 130 that the reset is complete andnormal I/O operations may continue. Suitable means for evaluation fortiming of notification of the host 130 is based on parameters such asnumber of pending commands in the device, current cache buffer size,NAND state, pending background operations, dirty entries in an FTL tableto be flushed to the NAND, and the like, that should be completed in thefront-end 115 during the reset, as well as estimated time for reset andre-initialization. It should be noted that the time for notifying thehost may be determined to be at a time prior to initiation ofre-initialization operations and to the back-end 120 completing itsreset operations.

In other embodiments the reset handler 110 doesn't evaluate a particulartime to notify the host 130, and instead generates a signal to notifythe host 130 that the reset is complete when front-end 115 has completedits reset operations, prior to start of re-initialization operations andcompletion of back-end 120 operations.

NVMe device controller 105 is depicted in FIG. 1 as having a number ofdiscrete processors, such as front-end processor 116, back-end processor121, and controller processor 140. However, suitable means for one ormore of these processor may be as a single processor, multipleprocessors, or one or more processors located remotely from NVMe devicecontroller 105 or NVMe device 100.

FIG. 2 depicts a flow diagram 200 describing an interleaved NVMe resetand re-initialization in accordance with embodiments of the disclosure.At 205, a reset command is issued. In some embodiments, the host 130, orother device outside of NVMe device 100, may issue the reset command,while in other embodiments the NVMe device controller 105 may issue thereset command.

At 210 reset handling time evaluation is carried out to determine a hostreset complete notification time based on pending activities in thefront-end 115 that need to be completed, and estimated timing requiredfor reset and reinitialization. The result of this evaluation may beused by the NVMe device controller 105 to determine when to report thatthe reset is complete to the host 130, while in parallel the NVMe device100 begins reinitialization and continues to process back-end resetoperations. In an alternate embodiment, reset handling time evaluationis not carried out, and instead a reset complete signal is provided tothe host 130 when the front-end 115 has completed its reset operations,before reinitialization operations are initiated, and in embodiments,before completion of back-end 120 reset operations.

At 215, front-end 115, which has had its reset handling operationslogically isolated from its reinitialization operations, andfunctionally isolated from the back-end 120, carries out front-end resethandling operations.

At 220, and in parallel with step 215, back-end 120, functionallyisolated from front-end 115, carries out back-end reset handlingoperations.

At 225, a determination is made as to whether or not front-end 115 hascompleted front-end reset handling operations. If not, the ‘no’ path isfollowed to allow front-end 115 to complete front-end reset handlingoperations. If the front-end reset handling operations are complete, theprocess continues to 230. In embodiments, this occurs in parallel withthe back-end 120 carrying out back-end reset handling operations.

At 230, a report is made to host 130 based on the reset evaluation. NVMedevice controller 105, once host reset notification time has beenreached, sends a signal to the host indicating that the reset iscomplete. This will occur even if back-end reset operations are notcomplete and will signal the start of reinitialization operations on thefront-end 115; these operations will continue in parallel.

In an alternate embodiment in which a host reset notification time hasnot been determined, the NVMe device controller 105 will send a signalto the host that the reset is complete once the front-end 115 resetoperations are complete. This will occur whether or not the back-endreset operations are complete, and initiate reinitialization operations.

At 235 the host 130 reinitializes the NVMe device 100. This may occur inparallel with back-end reset operations of step 220 and reinitializationoperations initiated at 230.

At 240, the host issues a doorbell write to an I/O submission queueindicating that an I/O command is pending.

At 245 NVMe controller 105 determines if back-end reset operations ofstep 220 are complete. If not, the back-end reset operations willcontinue and no commands will be fetched. If back-end reset operationsand reinitialization are complete, the process proceeds to step 250 inwhich commands from host 130 may be fetched and processed. In analternate embodiment, commands may be fetched from the host 130 beforecompleting back-end reset operations. In such an embodiment, thefront-end 115 will not sent any notification to the back-end 120 beforeall reset operations, including reinitialization, are complete.

At 250, the NVMe device 100 fetches commands from the host 130 forexecution.

FIG. 3 depicts an exemplary host system in which disclosed embodimentsmay be integrated and perform methods described herein, with respect toFIGS. 1 and 2.

Host System 300 includes a central processing unit (CPU) 302 connectedto data bus 304. CPU 302 is capable of processing computer-executableinstructions, such as may be stored for example, in memory 306 orstorage 308 that may include NVMe module 350 to perform the methodsdescribed herein, for example with respect to FIGS. 1 and 2. Inembodiments, host system 300 may be similar to aforementioned host 130.

Suitable means for memory 306 may be a single physical memory, multiplememories, as well as one or more memories located remotely from the hostsystem 300 and accessed via a network. Similarly suitable means forstorage 308 may be one or more physical storage devices may be utilized,and one or more physical storage devices may be located remotely fromhost system 300 and accessed via a network. One such physical storagedevice that comprises storage 308, in some embodiments, is NVMe module350.

Suitable means for CPU 302 in embodiments may be a single CPU, multipleCPU's, a single CPU having multiple cores, one or more CPU's locatedremotely from host system 300, one or more virtualized CPU's, or otherforms of processing architecture capable of executing computer-readableinstructions.

Host system 300 further includes, in embodiments, input/output (I/O)device(s) 310 and I/O device interface(s) 312, allowing host system 300to interface I/O devices 310, such as for example, keyboards, displays,mouse devices, pens, and other devices that allow for interaction withhost system 300. Note that host system 300 may connect with external I/Odevices through physical and wireless connections.

Host system 300 may further include a network interface 314, to providehost system 300 with access to external network 316 and concomitantly,external computing devices, components, and services.

Host system 300 further includes NVMe module 350, which in this exampleincludes an NVMe controller module 355 and a NAND module 353, a resethandling module 360, a reset handling evaluation module 363, a front-endmodule 365 that is functionally and/or logically separate from aback-end module 370, for performing operations described in connectionwith FIGS. 1 and 2.

FIG. 4 depicts a timing diagram 400 in accordance with embodiments ofthe disclosure.

At 410 a reset is issued to the NVMe device 100. The reset 410 may beissued by a host 130, or by the NVMe device 100 itself.

At 420, device reset handling is initiated by reset handler 110,logically dividing reset operations of the front-end 115, back-end 120,and reinitialization. At 430, front-end reset handling is initiated, andonce complete, at 440 the reset handler 110 provides an issue resetcomplete to the host 130.

At 450 NVMe device 100 reinitialization commences, in parallel withback-end reset handling 460.

I/O Command fetching 470 from the host may occur at any time prior tocompletion of either or both of back-end reset handling 460 and devicere-initialization 450. Commands fetched prior to completion of either ofthese will cause the front-end 115 to hold the commands until back-endreset handling 460 and device reinitialization 450 are completed.

The preceding description is provided to enable any person skilled inthe art to practice the various embodiments described herein. Theexamples discussed herein are not limiting of the scope, applicability,or embodiments set forth in the claims. Various modifications to theseembodiments will be readily apparent to those skilled in the art, andthe generic principles defined herein may be applied to otherembodiments. For example, changes may be made in the function andarrangement of elements discussed without departing from the scope ofthe disclosure. Various examples may omit, substitute, or add variousprocedures or components as appropriate. For instance, the methodsdescribed may be performed in an order different from that described,and various steps may be added, omitted, or combined. Also, featuresdescribed with respect to some examples may be combined in some otherexamples. For example, an apparatus may be implemented, or a method maybe practiced using any number of the aspects set forth herein. Inaddition, the scope of the disclosure is intended to cover such anapparatus or method that is practiced using other structure,functionality, or structure and functionality in addition to, or otherthan, the various aspects of the disclosure set forth herein. It shouldbe understood that any aspect of the disclosure disclosed herein may beembodied by one or more elements of a claim.

As used herein, a phrase referring to “at least one of” a list of itemsrefers to any combination of those items, including single members. Asan example, “at least one of: a, b, or c” is intended to cover a, b, c,a-b, a-c, b-c, and a-b-c, as well as any combination with multiples ofthe same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b,b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).

As used herein, the term “determining” encompasses a wide variety ofactions. For example, “determining” may include calculating, computing,processing, deriving, investigating, looking up (e.g., looking up in atable, a database or another data structure), ascertaining and the like.Also, “determining” may include receiving (e.g., receiving information),accessing (e.g., accessing data in a memory) and the like. Also,“determining” may include resolving, selecting, choosing, establishingand the like.

The methods disclosed herein comprise one or more steps or actions forachieving the methods. The method steps and/or actions may beinterchanged with one another without departing from the scope of theclaims. In other words, unless a specific order of steps or actions isspecified, the order and/or use of specific steps and/or actions may bemodified without departing from the scope of the claims. Further, thevarious operations of methods described above may be performed by anysuitable means capable of performing the corresponding functions. Themeans may include various hardware and/or software component(s) and/ormodule(s), including, but not limited to a circuit, an applicationspecific integrated circuit (ASIC), or processor. Generally, where thereare operations illustrated in figures, those operations may havecorresponding counterpart means-plus-function components with similarnumbering.

The various illustrative logical blocks, modules and circuits describedin connection with the present disclosure may be implemented orperformed with a general purpose processor, a digital signal processor(DSP), an application specific integrated circuit (ASIC), a fieldprogrammable gate array (FPGA) or other programmable logic device (PLD),discrete gate or transistor logic, discrete hardware components, or anycombination thereof designed to perform the functions described herein.A general-purpose processor may be a microprocessor, but in thealternative, the processor may be any commercially available processor,controller, microcontroller, or state machine. A processor may also beimplemented as a combination of computing devices, e.g., a combinationof a DSP and a microprocessor, a plurality of microprocessors, one ormore microprocessors in conjunction with a DSP core, or any other suchconfiguration.

A processing system may be implemented with a bus architecture. The busmay include any number of interconnecting buses and bridges depending onthe specific application of the processing system and the overall designconstraints. The bus may link together various circuits including aprocessor, machine-readable media, and input/output devices, amongothers. A user interface (e.g., keypad, display, mouse, joystick, etc.)may also be connected to the bus. The bus may also link various othercircuits such as timing sources, peripherals, voltage regulators, powermanagement circuits, and other circuit elements that are well known inthe art, and therefore, will not be described any further. The processormay be implemented with one or more general-purpose and/orspecial-purpose processors. Examples include microprocessors,microcontrollers, DSP processors, and other circuitry that can executesoftware. Those skilled in the art will recognize how best to implementthe described functionality for the processing system depending on theparticular application and the overall design constraints imposed on theoverall system.

If implemented in software, the functions may be stored or transmittedover as one or more instructions or code on a computer-readable medium.Software shall be construed broadly to mean instructions, data, or anycombination thereof, whether referred to as software, firmware,middleware, microcode, hardware description language, or otherwise.Computer-readable media include both computer storage media andcommunication media, such as any medium that facilitates the transfer ofa computer program from one place to another. The processor may beresponsible for managing the bus and general processing, including theexecution of software modules stored on the computer-readable storagemedia. A computer-readable storage medium may be coupled to a processorsuch that the processor can read information from, and write informationto, the storage medium. In the alternative, the storage medium may beintegral to the processor. By way of example, the computer-readablemedia may include a transmission line, a carrier wave modulated by data,and/or a computer readable storage medium with instructions storedthereon separate from the wireless node, all of which may be accessed bythe processor through the bus interface. Alternatively, or in addition,the computer-readable media, or any portion thereof, may be integratedinto the processor, such as the case may be with cache and/or generalregister files. Examples of machine-readable storage media may include,by way of example, RAM (Random Access Memory), flash memory, ROM (ReadOnly Memory), PROM (Programmable Read-Only Memory), EPROM (ErasableProgrammable Read-Only Memory), EEPROM (Electrically ErasableProgrammable Read-Only Memory), registers, magnetic disks, opticaldisks, hard drives, or any other suitable storage medium, or anycombination thereof. The machine-readable media may be embodied in acomputer-program product.

A software module may comprise a single instruction, or manyinstructions, and may be distributed over several different codesegments, among different programs, and across multiple storage media.The computer-readable media may comprise a number of software modules.The software modules include instructions that, when executed by anapparatus such as a processor, cause the processing system to performvarious functions. The software modules may include a transmissionmodule and a receiving module. Each software module may reside in asingle storage device or be distributed across multiple storage devices.By way of example, a software module may be loaded into RAM from a harddrive when a triggering event occurs. During the execution of thesoftware module, the processor may load some of the instructions intocache to increase access speed. One or more cache lines may then beloaded into a general register file for execution by the processor. Whenreferring to the functionality of a software module, it will beunderstood that such functionality is implemented by the processor whenexecuting instructions from that software module.

The following claims are not intended to be limited to the embodimentsshown herein but are to be accorded the full scope consistent with thelanguage of the claims. Within a claim, a reference to an element in thesingular is not intended to mean “one and only one” unless specificallyso stated, but rather “one or more.” Unless specifically statedotherwise, the term “some” refers to one or more. No claim element is tobe construed under the provisions of 35 U.S.C. § 112(f) unless theelement is expressly recited using the phrase “means for” or, in thecase of a method claim, the element is recited using the phrase “stepfor.” All structural and functional equivalents to the elements of thevarious aspects described throughout this disclosure that are known orlater come to be known to those of ordinary skill in the art areexpressly incorporated herein by reference and are intended to beencompassed by the claims. Moreover, nothing disclosed herein isintended to be dedicated to the public regardless of whether suchdisclosure is explicitly recited in the claims.

In following the systems and methods disclosed herein, timing of a resetof an NVMe device may become more predictable, enabling operations within a host to proceed in an efficient manner.

In one embodiment, a data storage device is disclosed. In embodiments,the data storage device may include a controller comprising instructionsthat, when executed by a processor, cause the controller to perform amethod of resetting the data storage device. In embodiments, the methodcomprises logically separating a set of front-end reset tasks from a setof back-end reset tasks, receiving a reset command from a host system,performing the set of front-end reset tasks and set of back-end resettasks in parallel upon receipt of the reset command. The method mayfurther comprise transmitting a reset complete signal to the host systemupon completion of the set of front-end reset tasks, and transmitting astorage device ready signal to the host system that indicates that thestorage device is in a condition to receive a command from the hostsystem. In embodiments, the method may further comprise receiving acommand from the host system and executing the command when the set ofback-end reset tasks are complete.

In another embodiment, a data storage system is disclosed. The datastorage system, in embodiments, includes an interface configured toreceive reset instructions from a host, a front-end module configured tocarry out front-end reset operations, and a back-end module configuredto carry out back-end reset operations. This system may further comprisea reset handler module configured to logically separate the front-endmodule from the back-end module, wherein the front-end reset operationsand back-end reset operations are carried out in parallel, and the resethandler module is configured to communicate with the host that resetoperations are complete upon completion of front-end operations.

In another embodiment, a data storage system is disclosed comprising acontroller that includes a processor for executing computer instructionsto reset the data storage system. In embodiments, the controller mayinclude a front-end module configured to carry out front-end resetoperations, a back-end module configured to carry out back-end resetoperations, and a means for logically separating the front-end resetoperations from the back-end reset operations, such that the front-endreset operations and back-end reset operations are carried out inparallel.

While the foregoing is directed to embodiments of the presentdisclosure, other and further embodiments of the disclosure may bedevised without departing from the basic scope thereof, and the scopethereof is determined by the claims that follow.

What is claimed is:
 1. A data storage device, comprising: a controllercomprising instructions that, when executed by a processor, cause thecontroller to perform a method of resetting the data storage device, themethod comprising: performing a set of front-end reset tasks and a setof back-end reset tasks in parallel upon receipt of a reset command;transmitting a reset complete signal to a host system upon completion ofthe set of front-end reset tasks; receiving a command from the hostsystem; and executing the command when the set of back-end reset tasksare complete.
 2. The data storage device of claim 1, wherein the set ofback-end reset tasks are not complete when the reset complete signal istransmitted.
 3. The data storage device of claim 1, further comprisingre-initialization of the storage device by the host system aftertransmitting the reset complete signal to the host system.
 4. The datastorage device of claim 1, wherein a storage device ready signal istransmitted to the host system after a delay time.
 5. The data storagedevice of claim 4, wherein the delay time comprises estimating with aprocessor, a time to complete one of the front-end reset tasks and theback-end reset tasks.
 6. The data storage device of claim 5, wherein thedelay time comprises estimating with a processor, a time to completeboth of the front-end reset tasks and back-end reset tasks.
 7. The datastorage device of claim 1, wherein the set of front-end reset taskscomprises one of resetting a register and resetting a queue, and the setof back-end reset tasks comprises writing to one of a NAND and a memory.8. A data storage system, comprising: a reset handler module configuredto logically separate a front-end module from a back-end module, whereinfront-end reset operations and back-end reset operations are carried outin parallel, and wherein the reset handler module configured tocommunicate with the host that reset operations are complete uponcompletion of front-end reset operations.
 9. The data storage system ofclaim 8, further comprising a reset handler evaluation module configuredto determine a reset-complete notification time to provide to a host.10. The data storage system of claim 9, wherein the reset-competenotification time is determined to be less than the time required tocarry out back-end reset operations.
 11. The data storage system ofclaim 9, wherein the reset-complete notification time is less than thetime required to carry out back-end reset operations and front-end resetoperations.
 12. The data storage system of claim 9, wherein the resethandler evaluation module is configured to determine the reset-completenotification time based at least on part on the completion of one of thefront-end reset operations and back-end reset operations.
 13. The datastorage system of claim 9, wherein the reset handler evaluation moduleis configured to determine the reset-complete notification time based atleast in part on the completion of both of the front-end resetoperations and back-end reset operations.
 14. The data storage system ofclaim 11, wherein at least one of the front-end reset operations used todetermine the reset-complete notification time is pending activities inthe data storage system at the time reset instructions are received fromthe host.
 15. The data storage system of claim 8, wherein the resethandler module communicates with a host that reset operations arecomplete prior to the completion of back-end reset operations.
 16. Thedata storage system of claim 15, wherein the data storage system isconfigured to provide doorbell access to the host prior to thecompletion of back-end reset operations.
 17. The data storage system ofclaim 16, wherein the data storage system is configured to not fetchcommands from the host until back-end reset operations are complete. 18.A data storage system, comprising: means for logically separatingfront-end reset operations from back-end reset operations; and means forexecuting the front-end reset operations and back-end reset operationsin parallel.
 19. The data storage system of claim 18, further comprisingmeans for notifying a host that at least one of the front-end resetoperations and back-end reset operations is complete.
 20. The datastorage system of claim 19, configured such that one of the front-endreset operations and back-end reset operations is not complete afternotifying the host.